1. Field of the Invention
This invention pertains to analog-to-digital conversion techniques. More specifically, this invention pertains to such techniques which are designed to enable a successive approximation register to generate data words which accurately represent, within a predetermined tolerance, an analog signal that can vary within a dynamic range that encompasses more bits than the successive approximation register can handle at one time.
2. Description of Prior Art
A successive approximation register is a semiconductor device which is designed for use in an analog-to-digital conversion system in order to convert an analog electrical signal to a digital data word expressed in parallel form. In such a system, the dynamic range of the analog signal to be expected is known in advance. This analog signal is first compared with a reference signal in a comparator, which may be an operational amplifier or other suitable device. Initially, the reference signal chosen is chosen to equal one-half of the maximum value which the analog electrical signal can be expected to reach. In the event that the analog signal equals or exceeds the reference signal so chosen, the comparator produces a logically high output. In the event that the analog signal is less than the reference signal so chosen, the comparator then produces a logically low output.
This comparison process is then repeated utilizing a reference signal that is chosen depending upon the results of the prior comparison. If the prior comparison indicates that the analog electrical signal is greater than a referenece signal equal to one-half the maximum value which the analog signal is expected to reach, the analog signal is then compared with a reference signal which is equal to three-fourths of the maximum value which the analog signal can be expected to reach. As before, the comparator will produce a logically high output when the analog signal exceeds this three-fourths value, and will produce a logically low signal otherwise. Conversely, in the event that the initial comparison indicated that the analog signal was less than one-half the maximum expected value, the analog signal would be compared with a reference signal equal to one-fourth of such maximum expected value, and a logically high or logically low output would be generated as before.
This comparison process is then repeated as many times as is necessary in order to achieve the desired accuracy of the analog-to-digital conversion. If only one such comparison is made, the resulting "1" (or logically high comparator output) or resulting "0" (logically low comparator output) will be only 50% accurate. A two-stage comparison process will be 25% accurate, and in general the accuracy of the conversion process will be equal to that percentage which corresponds to 1/2.sup.n, wherein n is equal to the number of comparisons performed in the conversion operation. Thus, an analog-to-digital conversion process which utilizes four such comparisons will have a tolerance of 1/16, or approximately 6%.
It will thus become evident that in order to retain the results of such comparisons, it is necessary to provide a semiconductor device which stores the 0's and 1's produced during the sequence of comparisons utilized in order to generate a digital data word which represents the value of the analog signal. For example, if a four-comparison process is used, the digital data word would be a binary four-placed number. If, for example, this number was 1111, then the analog signal would be equal to 15/16 of the maximum value which would ordinarily be expected.
Thus, successive approximation registers are now in existence which have a data input and a plurality of parallel data outputs, which parallel data outputs are arranged in a sequence going from a most significant bit or MSB, to a least significant bit or LSB. In, for example, a known successive approximation register, there may be eight parallel data outputs to enable the data resulting from an eight-step comparison process to be simultaneously registered and stored. Thus, a comparator would be connected to the data input of such a successive approximation register, and each time a comparison was performed a logically low or logically high signal would appear at a corresponding one of the parallel data outputs.
However, such successive approximation registers are not currently available with very large bit holding capacities. Thus, if such a successive approximation register is to be used in an analog-to-digital conversion system which is designed to convert an analog signal which may vary within a very wide dynamic range, inaccuracy will result. For example, modern photographic equipment such as still cameras and motion-picture cameras can distinguish between eighteen separate intensities of light, in which each intensity is double the intensity of the previous one. Broadly put, a modern camera can be utilized in a wide range of illumination intensities, ranging from the brilliant illumination of arc lights to perhaps the illumination provided by a burning match. With such a wide dynamic range encompassed by the illumination which can be expected, which dynamic range requires eighteen bits in order to express it, a successive approximation register which holds eight bits will not operate properly if used in a conventional fashion in the automatic exposure system of such a camera. For example, it would be prefectly possible for an illumination to be used which is sufficiently low so that all the parallel data outputs of the successive approximation register would read 0, while the light intensity available would still be sufficient to enable the camera to be used.
However, when a successive approximation register is to be used in such a camera, it is not necessary that the analog-to-digital conversion be extraordinarily accurate. Since a modern motion picture camera can accept a tolerance of one-tenth of a stop, which tolerance corresponds to approximately a 7% variation in light intensity, it is only necessary that the digital data word to be used in the camera exposure system, have an accuracy equal to or only slightly greater than 7%. A digital data word of only four bits would thus suffice in terms of exposure accuracy, as long as the weight to be accorded this four-bit digital data word were known.
In other words, although the illumination of a scene to be photographed has such a broad dynamic range that eighteen bits are required in order to accurately describe the entire dynamic range exactly, once the portion of that dynamic range which is actually being measured is known, it is not necessary to measure the exact value of the illumination to an accuracy of greater than 7%. Thus, as long as it is known in what portion of the dynamic range the camera is actually to be used, only four bits are actually required.
Because analog-to-digital converters utilizing successive approximation registers can be made to operate at a rapid rate and can be made to produce conversions with a high degree of accuracy, it would be desirable to provide a system which would allow a conventional successive approximation register to be used in a conversion system of this type.